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Tag Archives: IP
A panel of private company IP founders from CAST, IPExtreme, Methods2Business, and Recore Systems reveal their strategies for building thriving companies.
A panel of global semiconductor IP founders reveals their strategies for building companies that can thrive in a competitive market. What advice will they offer to today’s entrepeneurs? What is the best way to handle growing pains? Which exit strategies might actually work? These are just some of the questions that will be address by Hal Barbour of CAST; Warren Savage of IPextreme; Marleen Boonen of Methods2Business; and Dirk Logie of Recore Systems. Gabrièle Saucier of Design and Reuse is the panel’s chair. John Blyler of Extension Media will be the moderator. What follows is a position statement from the panelist in preparation for this discussion. – JB
Panel Description: “The Making and Selling of IP Businesses – Private Companies” – In this session, we will have two panels to hear perspectives from both sides. The private company panel will discuss with founders their strategies for building a company that can thrive in a competitive market. The public companies panel will discuss their approach toward acquisitions and some of the things that private companies should know that can increase their valuation.
Read the complete post on the System Design Engineering site.
Recent announcements by the semiconductor foundry and chip design tool industries confirm the growing viability of Silicon-on-Insulator technology.
The recent announcement that Samsung Electronics would source SOI manufacturing is welcome news to the chip community. But does this additional manufacturing capability mean that EDA and IP tool vendors will give greater support to the SoI technology, as Peter Clark suggests in a recent article? Does the gain of the Samsung foundry suggest a loss of support from the GLOBALFOUNDRIES? Let’s focus on the first question.
Read the complete post on the Chipestimate.com IP-Insider blog.
June 1 – 5, 2014
Moscone Center, San Francisco, CA
At DAC 2014, ChipEstimate.com will present the latest solutions from the leading IP suppliers and foundries on the IP Talks! stage. Watch this space to see the schedule of participating partners and plan your DAC 2014 agenda. Also, be sure to join us in booth 1533 for hands-on demonstrations of IP exploration and chip estimation, and discover how to estimate your next chip’s size, power, and cost.
The Low-Power Engineering (LPE) portal asked the experts for help in detailing the best practices to help digital designers incorporate analog, mixed signal and RF functionality into their System-on-Chips (SoC). What follows is a compendium of inputs from Diya Soubra, CPU Product Manager, Processor Division and Joseph Yiu, Embedded Technology Specialist at ARM; Qi Wang,Technical Marketing Group Director and Mladen Nizic, Engineering Director for Mixed Signal Solutions at Cadence Design Systems.
Blyler: What are the best practices for EDA chip-level IoT mixed signal and microcontroller designs?
- Use of power aware verification early and throughout in the project, e.g., power aware simulation with Si2 Common Power Format (CPF) (and/or IEEE-Accellera Unified Power Format (UPF)). Power aware verification is not just for low power simulations but also for various system level simulations.
- Use the right model for mixed signal simulation (trade off between accuracy and simulation speed)
- Power quality check. Verification of power constraints/budgets in the early stage of the design can help you to find corner cases in power management schemes.
Read the complete post on the Low Power Engineering site.