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Tag Archives: Cadence

Will Stage 4 Mark the End of Semiconductor EDA Consolidation?

Everyone talks about the increasing consolidation of the EDA tools market, but few provide quantified data for accurate predictions.

Mergers won’t guarantee the survival of chipmakers, explained Microchip’s CEO Steve Sanghi in a recentEETimes article by Rick Merritt. “Mergers are marking the chip industry’s maturity as companies get bigger to survive harsher times ahead.”

The consolidation of the EDA market is nothing new. The past three years have been a particularly active period. But consolidation can not continue forever in a market where venture-capital funding is declining for semiconductor start-ups. Is there any way to gauge the level of consolidation in the market as a whole and in particular the EDA tools segment? Further, is there a level of consolidation at which IP design and reuse will be adversely affected? We’ll start with the first question.

Read the entire post on the Chipestimate.com “IP Insider

Are Semiconductor Fabs and EDA-IP Ready for FD-SOI?

Recent announcements by the semiconductor foundry and chip design tool industries confirm the growing viability of Silicon-on-Insulator technology.

The recent announcement that Samsung Electronics would source SOI manufacturing is welcome news to the chip community. But does this additional manufacturing capability mean that EDA and IP tool vendors will give greater support to the SoI technology, as Peter Clark suggests in a recent article? Does the gain of the Samsung foundry suggest a loss of support from the GLOBALFOUNDRIES? Let’s focus on the first question.

Read the complete post on the Chipestimate.com IP-Insider blog.

Best Practices for Mixed Signal, RF and Microcontroller IoT

The Low-Power Engineering (LPE) portal asked the experts for help in detailing the best practices to help digital designers incorporate analog, mixed signal and RF functionality into their System-on-Chips (SoC). What follows is a compendium of inputs from Diya Soubra, CPU Product Manager, Processor Division and Joseph Yiu, Embedded Technology Specialist at ARM; Qi Wang,Technical Marketing Group Director and Mladen Nizic, Engineering Director for Mixed Signal Solutions at Cadence Design Systems.

Blyler: What are the best practices for EDA chip-level IoT mixed signal and microcontroller designs?

Joseph Yiu:
- Use of power aware verification early and throughout in the project, e.g., power aware simulation with Si2 Common Power Format (CPF) (and/or IEEE-Accellera Unified Power Format (UPF)). Power aware verification is not just for low power simulations but also for various system level simulations.
- Use the right model for mixed signal simulation (trade off between accuracy and simulation speed)
- Power quality check. Verification of power constraints/budgets in the early stage of the design can help you to find corner cases in power management schemes.

Read the complete post  on the Low Power Engineering site.