Home » Tag Archives: ARM

Tag Archives: ARM

Security Levels the IoT Device and Server Landscape

Best practices, standards and a diverse ecosystem are essential for embedded developers to mitigate threats such as stack overflows and software backdoors.

What are the best practices when designing for device through server IoT security systems? This question was put to the experts at ARM, including Marc Canel, Vice President, Security Technologies; Jeff Underhill, Director of Server Programs; and Joakim Bech, Technical Lead for Security Working Group at Linaro. What follows is a portion of those interviews. – JB

Blyler: Security for the Internet of Things (IoT) spans everything from end-point sensors to connected devices, aggregated gateways, and middleware – all the way to servers. How can embedded designers deal with all the inherent complexity?

Bech: I think it’s impossible to get a detailed understanding in all areas. It is simply too much to handle. But luckily, you normally don’t have to focus on all IoT devices at the same time. Under normal conditions, the embedded designers work with a limited set of products in a specific area. The tricky part is when these devices develop their own communication that result in an un-tested area where you could potentially have both bugs and security flaws to an even greater extent than standard protocols. Therefore, if possible, it’s almost always better and preferable to adhere to a predefined standard, instead of inventing new protocols.

IoT vs. Traditional Embedded for Analog, Low Power and Security

In Part III, technology leaders from STMicro, Atmel, Mouser, Synopsys, Movea, and ARM, define the big challenges in IoT – mixed signal, low power and security.

Will the Internet-of-Things (IoT) bring new analog integration, low power and security challenges to traditional SoC and embedded designs? To answer these questions, System Design Engineering sat down Bernard Kasser, Director Security R&D, Advanced System Technology, STMicroelectronic; Bob Martin, Senior Manager Microcontroller Group Central Applications, Atmel; Kevin Parmenter, Director of Technical Resources, Mouser; Steve Smith, Senior Director of Marketing, AMS Group, Synopsys; Cyrille Soubeyrat, VP of Engineering at Movea; and Diya Soubra, CPU Product Marketing Manager, ARM. What follows are excerpts from that discussion. – JB

Analog Designers Face Low Power Challenges

Can mixed signal designs achieve the low power needed by today’s tightly integrated SoCs and embedded IoT communication systems?

System level power budgets are affected by SoC integration. Setting aside the digital scaling benefits of smaller geometric nodes, leading edge SoCs achieve higher performance and tighter integration with decreased voltage levels at a cost. If power is assumed to be constant, then that cost is the increased current flow (P=VI) delivered to an ever larger number of processor cores. That’s why SoC power delivery and distribution remain a major challenge for chip architects, designers and verification engineers.

As with digital engineers, analog and mixed signal power designers must consider ways to lower power consumption early in the design phase. Beyond that consideration, there are several common ways to reduce the analog mixed signal portion of a power budget. These ways include low-power transmitter architectures; analog signal processing in low-voltage domains; and sleep mode power reduction. (ARM’s Diya Soubra takes about mixed signal sleep modes in, “Digital Designers Grapple with Analog Mixed Signal Designs.”)

Read the complete post on the System Design Engineering site.

Experts Share Unique Challenges in Wearable Designs

Wearable devices will add a new twist to traditional embedded designs according to experts from ARM, Freescale, HillCrest Labs, STMicr, Imec and Koinix.

Wearable technology design presents challenges different from other embedded markets. To understand these challenges, “System Design Engineering” talked with James Bruce, Director Mobile Solutions forARM; Mike Stanley, Systems Engineer at Freescale; Daniel Chaitow, Marketing Communications Manager at Hillcrest Labs; Jay Esfandyari, Director of Global Product Marketing at STMicroelectronics; Siebren Schaafsma, Team Leader at Holst Centre and Imec, and; Thea Rejman, Financial Analyst at Kionix, Inc. What follows is a portion of that conversation. – JB

Read complete post on the System Design Engineering site.

Best Practices for Mixed Signal, RF and Microcontroller IoT

The Low-Power Engineering (LPE) portal asked the experts for help in detailing the best practices to help digital designers incorporate analog, mixed signal and RF functionality into their System-on-Chips (SoC). What follows is a compendium of inputs from Diya Soubra, CPU Product Manager, Processor Division and Joseph Yiu, Embedded Technology Specialist at ARM; Qi Wang,Technical Marketing Group Director and Mladen Nizic, Engineering Director for Mixed Signal Solutions at Cadence Design Systems.

Blyler: What are the best practices for EDA chip-level IoT mixed signal and microcontroller designs?

Joseph Yiu:
- Use of power aware verification early and throughout in the project, e.g., power aware simulation with Si2 Common Power Format (CPF) (and/or IEEE-Accellera Unified Power Format (UPF)). Power aware verification is not just for low power simulations but also for various system level simulations.
- Use the right model for mixed signal simulation (trade off between accuracy and simulation speed)
- Power quality check. Verification of power constraints/budgets in the early stage of the design can help you to find corner cases in power management schemes.

Read the complete post  on the Low Power Engineering site.