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Will Stage 4 Mark the End of Semiconductor EDA Consolidation?

Everyone talks about the increasing consolidation of the EDA tools market, but few provide quantified data for accurate predictions.

Mergers won’t guarantee the survival of chipmakers, explained Microchip’s CEO Steve Sanghi in a recentEETimes article by Rick Merritt. “Mergers are marking the chip industry’s maturity as companies get bigger to survive harsher times ahead.”

The consolidation of the EDA market is nothing new. The past three years have been a particularly active period. But consolidation can not continue forever in a market where venture-capital funding is declining for semiconductor start-ups. Is there any way to gauge the level of consolidation in the market as a whole and in particular the EDA tools segment? Further, is there a level of consolidation at which IP design and reuse will be adversely affected? We’ll start with the first question.

Read the entire post on the Chipestimate.com “IP Insider

Electronic Industry Veteran Tech Journalist Exits Extension Media

John Blyler, Chief Content Officer, seeks to combine online media, university teaching and engineering experiences.

July 8, 2014 – Portland, Ore. – After 10 years as VP, Chief Content Officer at Extension Media, John Blyler is leaving to pursue other endeavors. While not fully disclosing his plans until the end of August, Blyler will remain involved in the world of semiconductors, systems hardware-software engineering and advanced technologies.

Blyler is a sponsored writer for the ARM® [NASDAQ: ARMH] Connected (Software) Community and on the Chipestimate.com IP Insider blog. He is the author of several technical books for Elsevier, IEEE/Wiley and SAE.  Blyler remains an affiliate professor of graduate-level systems engineering at Portland State University and an established public speaker on technology and science.

“As the industry continues to rapidly evolve, so must the ways in which we engage and add value,” said Blyler. “My background in engineering physics, as a journalist and at the university allows me to connect with a variety of professionals and companies in valuable ways. In turn, this network and experience has convinced me to focus on larger electronics systems, both in a hardware-software sense but also the often-difficult collaboration between cross-disciplinary systems. As you might imagine, these interface areas are where the biggest gaps in our tools and process flows occur.  I want to be a part of the larger effort to solve these problems – through editorial coverage, unique online distribution strategies, educational course-seminar offerings and engineering engagements.”

Specific details about new media and technical educational services will be disclosed in late August. To review some of Blyler’s past work, please visit JohnBlyler.com.  He can be reached at j.blyler@ieee.org or on Twitter or LinkedIn.


Media Contact:
Susan Cain
Cain Communications


Analog Designers Face Low Power Challenges

Can mixed signal designs achieve the low power needed by today’s tightly integrated SoCs and embedded IoT communication systems?

System level power budgets are affected by SoC integration. Setting aside the digital scaling benefits of smaller geometric nodes, leading edge SoCs achieve higher performance and tighter integration with decreased voltage levels at a cost. If power is assumed to be constant, then that cost is the increased current flow (P=VI) delivered to an ever larger number of processor cores. That’s why SoC power delivery and distribution remain a major challenge for chip architects, designers and verification engineers.

As with digital engineers, analog and mixed signal power designers must consider ways to lower power consumption early in the design phase. Beyond that consideration, there are several common ways to reduce the analog mixed signal portion of a power budget. These ways include low-power transmitter architectures; analog signal processing in low-voltage domains; and sleep mode power reduction. (ARM’s Diya Soubra takes about mixed signal sleep modes in, “Digital Designers Grapple with Analog Mixed Signal Designs.”)

Read the complete post on the System Design Engineering site.

Too Much Verification? Jasper’s CEO Kathryn Kranen Responds

Is there a verification gap? Or is it that too much time is being spent inefficiently on verification? Kathryn Kranen, President and CEO of Jasper Design Automation, believes the latter. Customers have told her about too many wasted simulation, engineering, and debug cycles that are being spent to achieve the desired levels of design quality.

Kranen believes that the verification gap is less about an excess of verification and more about an excess of time spent on verification.

Read the complete post on the System Design Engineering site.

Business Secrets from Private Semiconductor IP Companies

A panel of private company IP founders from CAST, IPExtreme, Methods2Business, and Recore Systems reveal their strategies for building thriving companies.

A panel of global semiconductor IP founders reveals their strategies for building companies that can thrive in a competitive market. What advice will they offer to today’s entrepeneurs? What is the best way to handle growing pains? Which exit strategies might actually work? These are just some of the questions that will be address by Hal Barbour of CAST; Warren Savage of IPextreme; Marleen Boonen of Methods2Business; and Dirk Logie of Recore Systems. Gabrièle Saucier of Design and Reuse is the panel’s chair. John Blyler of Extension Media will be the moderator. What follows is a position statement from the panelist in preparation for this discussion. – JB

Panel Description: “The Making and Selling of IP Businesses – Private Companies” – In this session, we will have two panels to hear perspectives from both sides. The private company panel will discuss with founders their strategies for building a company that can thrive in a competitive market. The public companies panel will discuss their approach toward acquisitions and some of the things that private companies should know that can increase their valuation.

Read the complete post on the System Design Engineering site.

Experts Share Unique Challenges in Wearable Designs

Wearable devices will add a new twist to traditional embedded designs according to experts from ARM, Freescale, HillCrest Labs, STMicr, Imec and Koinix.

Wearable technology design presents challenges different from other embedded markets. To understand these challenges, “System Design Engineering” talked with James Bruce, Director Mobile Solutions forARM; Mike Stanley, Systems Engineer at Freescale; Daniel Chaitow, Marketing Communications Manager at Hillcrest Labs; Jay Esfandyari, Director of Global Product Marketing at STMicroelectronics; Siebren Schaafsma, Team Leader at Holst Centre and Imec, and; Thea Rejman, Financial Analyst at Kionix, Inc. What follows is a portion of that conversation. – JB

Read complete post on the System Design Engineering site.

Best Practices for Mixed Signal, RF and Microcontroller IoT

The Low-Power Engineering (LPE) portal asked the experts for help in detailing the best practices to help digital designers incorporate analog, mixed signal and RF functionality into their System-on-Chips (SoC). What follows is a compendium of inputs from Diya Soubra, CPU Product Manager, Processor Division and Joseph Yiu, Embedded Technology Specialist at ARM; Qi Wang,Technical Marketing Group Director and Mladen Nizic, Engineering Director for Mixed Signal Solutions at Cadence Design Systems.

Blyler: What are the best practices for EDA chip-level IoT mixed signal and microcontroller designs?

Joseph Yiu:
- Use of power aware verification early and throughout in the project, e.g., power aware simulation with Si2 Common Power Format (CPF) (and/or IEEE-Accellera Unified Power Format (UPF)). Power aware verification is not just for low power simulations but also for various system level simulations.
- Use the right model for mixed signal simulation (trade off between accuracy and simulation speed)
- Power quality check. Verification of power constraints/budgets in the early stage of the design can help you to find corner cases in power management schemes.

Read the complete post  on the Low Power Engineering site.