Home » Author Archives: John Blyler

Author Archives: John Blyler

比较“嵌入式蜂窝设计”与“嵌入式 WiFi 设计”

Another translated article for my Chinese colleagues and readers (with thanks to Song Bin 宋斌) 

嵌入式开发人员应知道蜂窝(Cellular)连接和 WiFi 连接之间的差异,尤其是由原型制作转为生产设计阶段时这两种连接类型的差异。

 WiFi 连接相比,将蜂窝连接添加至嵌入式设计是否更为困难?如何从原型设计转化为生产即用设备呢?为回答诸多这些问题,我采访了 ARM 运营商关系部产品经理 Richard
Stamvik
以下是访谈部分。– JB

Blyler蜂窝连接是如何在诸如机器到机器 (M2M)和物联网 (IoT) 等应用的嵌入式开发空间中发挥作用?

Stamvik:作为产品营销团队的一份子,我帮助跟踪蜂窝网络空间的发展。对我们而言,产品营销是面向硅片供应商之外的客户,如设备供应商、软件开发人员和蜂窝网络运营商等。这一点十分重要,因为运营商是我们了解消费者需求的最亲密合作伙伴。

Security Levels the IoT Device and Server Landscape

Best practices, standards and a diverse ecosystem are essential for embedded developers to mitigate threats such as stack overflows and software backdoors.

What are the best practices when designing for device through server IoT security systems? This question was put to the experts at ARM, including Marc Canel, Vice President, Security Technologies; Jeff Underhill, Director of Server Programs; and Joakim Bech, Technical Lead for Security Working Group at Linaro. What follows is a portion of those interviews. – JB

Blyler: Security for the Internet of Things (IoT) spans everything from end-point sensors to connected devices, aggregated gateways, and middleware – all the way to servers. How can embedded designers deal with all the inherent complexity?

Bech: I think it’s impossible to get a detailed understanding in all areas. It is simply too much to handle. But luckily, you normally don’t have to focus on all IoT devices at the same time. Under normal conditions, the embedded designers work with a limited set of products in a specific area. The tricky part is when these devices develop their own communication that result in an un-tested area where you could potentially have both bugs and security flaws to an even greater extent than standard protocols. Therefore, if possible, it’s almost always better and preferable to adhere to a predefined standard, instead of inventing new protocols.

IoT vs. Traditional Embedded for Analog, Low Power and Security

In Part III, technology leaders from STMicro, Atmel, Mouser, Synopsys, Movea, and ARM, define the big challenges in IoT – mixed signal, low power and security.

Will the Internet-of-Things (IoT) bring new analog integration, low power and security challenges to traditional SoC and embedded designs? To answer these questions, System Design Engineering sat down Bernard Kasser, Director Security R&D, Advanced System Technology, STMicroelectronic; Bob Martin, Senior Manager Microcontroller Group Central Applications, Atmel; Kevin Parmenter, Director of Technical Resources, Mouser; Steve Smith, Senior Director of Marketing, AMS Group, Synopsys; Cyrille Soubeyrat, VP of Engineering at Movea; and Diya Soubra, CPU Product Marketing Manager, ARM. What follows are excerpts from that discussion. – JB

Will Stage 4 Mark the End of Semiconductor EDA Consolidation?

Everyone talks about the increasing consolidation of the EDA tools market, but few provide quantified data for accurate predictions.

Mergers won’t guarantee the survival of chipmakers, explained Microchip’s CEO Steve Sanghi in a recentEETimes article by Rick Merritt. “Mergers are marking the chip industry’s maturity as companies get bigger to survive harsher times ahead.”

The consolidation of the EDA market is nothing new. The past three years have been a particularly active period. But consolidation can not continue forever in a market where venture-capital funding is declining for semiconductor start-ups. Is there any way to gauge the level of consolidation in the market as a whole and in particular the EDA tools segment? Further, is there a level of consolidation at which IP design and reuse will be adversely affected? We’ll start with the first question.

Read the entire post on the Chipestimate.com “IP Insider

Electronic Industry Veteran Tech Journalist Exits Extension Media

John Blyler, Chief Content Officer, seeks to combine online media, university teaching and engineering experiences.

July 8, 2014 – Portland, Ore. – After 10 years as VP, Chief Content Officer at Extension Media, John Blyler is leaving to pursue other endeavors. While not fully disclosing his plans until the end of August, Blyler will remain involved in the world of semiconductors, systems hardware-software engineering and advanced technologies.

Blyler is a sponsored writer for the ARM® [NASDAQ: ARMH] Connected (Software) Community and on the Chipestimate.com IP Insider blog. He is the author of several technical books for Elsevier, IEEE/Wiley and SAE.  Blyler remains an affiliate professor of graduate-level systems engineering at Portland State University and an established public speaker on technology and science.

“As the industry continues to rapidly evolve, so must the ways in which we engage and add value,” said Blyler. “My background in engineering physics, as a journalist and at the university allows me to connect with a variety of professionals and companies in valuable ways. In turn, this network and experience has convinced me to focus on larger electronics systems, both in a hardware-software sense but also the often-difficult collaboration between cross-disciplinary systems. As you might imagine, these interface areas are where the biggest gaps in our tools and process flows occur.  I want to be a part of the larger effort to solve these problems – through editorial coverage, unique online distribution strategies, educational course-seminar offerings and engineering engagements.”

Specific details about new media and technical educational services will be disclosed in late August. To review some of Blyler’s past work, please visit JohnBlyler.com.  He can be reached at j.blyler@ieee.org or on Twitter or LinkedIn.

 

Media Contact:
Susan Cain
Cain Communications
408-393-4794
scain@caincom.com

MarketWatch

Analog Designers Face Low Power Challenges

Can mixed signal designs achieve the low power needed by today’s tightly integrated SoCs and embedded IoT communication systems?

System level power budgets are affected by SoC integration. Setting aside the digital scaling benefits of smaller geometric nodes, leading edge SoCs achieve higher performance and tighter integration with decreased voltage levels at a cost. If power is assumed to be constant, then that cost is the increased current flow (P=VI) delivered to an ever larger number of processor cores. That’s why SoC power delivery and distribution remain a major challenge for chip architects, designers and verification engineers.

As with digital engineers, analog and mixed signal power designers must consider ways to lower power consumption early in the design phase. Beyond that consideration, there are several common ways to reduce the analog mixed signal portion of a power budget. These ways include low-power transmitter architectures; analog signal processing in low-voltage domains; and sleep mode power reduction. (ARM’s Diya Soubra takes about mixed signal sleep modes in, “Digital Designers Grapple with Analog Mixed Signal Designs.”)

Read the complete post on the System Design Engineering site.

Chip Testing Continuum Gets New Voice

Former EDA industry expert makes the case for pre-silicon testing using post-silicon tools. What part will IP play? Will design and test languages be a problem? Most engineers typically think of traditional test equipment as stand alone bulky oscilloscopes, digital-voltage-meters, logic analyzers and the like. But the trend over the last several decades has been toward modular test systems based on software. Today, modular boxes are used to perform every test function imaginable, from signal generator, spectrum analyzer, digital data source, to buss monitoring and control. These modules are connected together in a buss oriented backplane, controlled by software on the front-end. Read the complete post on the Chipestimate.com IP-Insider blog.  

Too Much Verification? Jasper’s CEO Kathryn Kranen Responds

Is there a verification gap? Or is it that too much time is being spent inefficiently on verification? Kathryn Kranen, President and CEO of Jasper Design Automation, believes the latter. Customers have told her about too many wasted simulation, engineering, and debug cycles that are being spent to achieve the desired levels of design quality.

Kranen believes that the verification gap is less about an excess of verification and more about an excess of time spent on verification.

Read the complete post on the System Design Engineering site.

Business Secrets from Private Semiconductor IP Companies

A panel of private company IP founders from CAST, IPExtreme, Methods2Business, and Recore Systems reveal their strategies for building thriving companies.

A panel of global semiconductor IP founders reveals their strategies for building companies that can thrive in a competitive market. What advice will they offer to today’s entrepeneurs? What is the best way to handle growing pains? Which exit strategies might actually work? These are just some of the questions that will be address by Hal Barbour of CAST; Warren Savage of IPextreme; Marleen Boonen of Methods2Business; and Dirk Logie of Recore Systems. Gabrièle Saucier of Design and Reuse is the panel’s chair. John Blyler of Extension Media will be the moderator. What follows is a position statement from the panelist in preparation for this discussion. – JB

Panel Description: “The Making and Selling of IP Businesses – Private Companies” – In this session, we will have two panels to hear perspectives from both sides. The private company panel will discuss with founders their strategies for building a company that can thrive in a competitive market. The public companies panel will discuss their approach toward acquisitions and some of the things that private companies should know that can increase their valuation.

Read the complete post on the System Design Engineering site.