Is there a verification gap? Or is it that too much time is being spent inefficiently on verification? Kathryn Kranen, President and CEO of Jasper Design Automation, believes the latter. Customers have told her about too many wasted simulation, engineering, and debug cycles that are being spent to achieve the desired levels of design quality.
Kranen believes that the verification gap is less about an excess of verification and more about an excess of time spent on verification.
Read the complete post on the System Design Engineering site.